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<div class="header">
  <div class="headertitle"><div class="title">TIM Master Mode Selection 2 (TRGO2) <div class="ingroups"><a class="el" href="group___s_t_m32_h7xx___h_a_l___driver.html">STM32H7xx_HAL_Driver</a> &raquo; <a class="el" href="group___t_i_m.html">TIM</a> &raquo; <a class="el" href="group___t_i_m___exported___constants.html">TIM Exported Constants</a></div></div></div>
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<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 id="header-define-members" class="groupheader"><a id="define-members" name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga1cbae68386015bde2e2087787d31a77f" id="r_ga1cbae68386015bde2e2087787d31a77f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga1cbae68386015bde2e2087787d31a77f">TIM_TRGO2_RESET</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memitem:gab9344703b3c1a7936f6b500a6bc26cb9" id="r_gab9344703b3c1a7936f6b500a6bc26cb9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gab9344703b3c1a7936f6b500a6bc26cb9">TIM_TRGO2_ENABLE</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga07efe60d8d7305b78085233ddaecb990">TIM_CR2_MMS2_0</a></td></tr>
<tr class="memitem:ga7c09a032f333bd3c1896e53f8c476303" id="r_ga7c09a032f333bd3c1896e53f8c476303"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga7c09a032f333bd3c1896e53f8c476303">TIM_TRGO2_UPDATE</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga0248e35956d0d22ac66dcd67aab317c5">TIM_CR2_MMS2_1</a></td></tr>
<tr class="memitem:ga6199721bcb0eb5f89dcd0b1055f7376f" id="r_ga6199721bcb0eb5f89dcd0b1055f7376f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga6199721bcb0eb5f89dcd0b1055f7376f">TIM_TRGO2_OC1</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga0248e35956d0d22ac66dcd67aab317c5">TIM_CR2_MMS2_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga07efe60d8d7305b78085233ddaecb990">TIM_CR2_MMS2_0</a>)</td></tr>
<tr class="memitem:gabe44de11cdf3f6d151b0d4a4945db092" id="r_gabe44de11cdf3f6d151b0d4a4945db092"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gabe44de11cdf3f6d151b0d4a4945db092">TIM_TRGO2_OC1REF</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gaa49670c71a446e5201994716b08b1527">TIM_CR2_MMS2_2</a></td></tr>
<tr class="memitem:gaaa5b56f4c834853ccf048399f77fbb3b" id="r_gaaa5b56f4c834853ccf048399f77fbb3b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaaa5b56f4c834853ccf048399f77fbb3b">TIM_TRGO2_OC2REF</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gaa49670c71a446e5201994716b08b1527">TIM_CR2_MMS2_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga07efe60d8d7305b78085233ddaecb990">TIM_CR2_MMS2_0</a>)</td></tr>
<tr class="memitem:ga670369673955ede3e33074ad1897c64a" id="r_ga670369673955ede3e33074ad1897c64a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga670369673955ede3e33074ad1897c64a">TIM_TRGO2_OC3REF</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gaa49670c71a446e5201994716b08b1527">TIM_CR2_MMS2_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga0248e35956d0d22ac66dcd67aab317c5">TIM_CR2_MMS2_1</a>)</td></tr>
<tr class="memitem:gaa307bb2aa7beb9f0ea43247a38ca7b36" id="r_gaa307bb2aa7beb9f0ea43247a38ca7b36"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaa307bb2aa7beb9f0ea43247a38ca7b36">TIM_TRGO2_OC4REF</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gaa49670c71a446e5201994716b08b1527">TIM_CR2_MMS2_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga0248e35956d0d22ac66dcd67aab317c5">TIM_CR2_MMS2_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga07efe60d8d7305b78085233ddaecb990">TIM_CR2_MMS2_0</a>)</td></tr>
<tr class="memitem:ga9609da1787a7dcde257de6f96dabed4c" id="r_ga9609da1787a7dcde257de6f96dabed4c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga9609da1787a7dcde257de6f96dabed4c">TIM_TRGO2_OC5REF</a>&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga3503937610adbf78153c1fcfa4bcd6ea">TIM_CR2_MMS2_3</a></td></tr>
<tr class="memitem:gae88c0c9c55ffb739dada0bdea37a809d" id="r_gae88c0c9c55ffb739dada0bdea37a809d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gae88c0c9c55ffb739dada0bdea37a809d">TIM_TRGO2_OC6REF</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga3503937610adbf78153c1fcfa4bcd6ea">TIM_CR2_MMS2_3</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga07efe60d8d7305b78085233ddaecb990">TIM_CR2_MMS2_0</a>)</td></tr>
<tr class="memitem:ga0916f567135c5ee60031da2d146ad10b" id="r_ga0916f567135c5ee60031da2d146ad10b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga0916f567135c5ee60031da2d146ad10b">TIM_TRGO2_OC4REF_RISINGFALLING</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga3503937610adbf78153c1fcfa4bcd6ea">TIM_CR2_MMS2_3</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga0248e35956d0d22ac66dcd67aab317c5">TIM_CR2_MMS2_1</a>)</td></tr>
<tr class="memitem:gaefa63d8189e6e6fcd592fcf4af8aa416" id="r_gaefa63d8189e6e6fcd592fcf4af8aa416"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#gaefa63d8189e6e6fcd592fcf4af8aa416">TIM_TRGO2_OC6REF_RISINGFALLING</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga3503937610adbf78153c1fcfa4bcd6ea">TIM_CR2_MMS2_3</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga0248e35956d0d22ac66dcd67aab317c5">TIM_CR2_MMS2_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga07efe60d8d7305b78085233ddaecb990">TIM_CR2_MMS2_0</a>)</td></tr>
<tr class="memitem:ga367b1addfd2f36bb8ed29e8e70e57024" id="r_ga367b1addfd2f36bb8ed29e8e70e57024"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga367b1addfd2f36bb8ed29e8e70e57024">TIM_TRGO2_OC4REF_RISING_OC6REF_RISING</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga3503937610adbf78153c1fcfa4bcd6ea">TIM_CR2_MMS2_3</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gaa49670c71a446e5201994716b08b1527">TIM_CR2_MMS2_2</a>)</td></tr>
<tr class="memitem:ga202fe63f92ca564cb18995a11b3946b2" id="r_ga202fe63f92ca564cb18995a11b3946b2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga202fe63f92ca564cb18995a11b3946b2">TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga3503937610adbf78153c1fcfa4bcd6ea">TIM_CR2_MMS2_3</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gaa49670c71a446e5201994716b08b1527">TIM_CR2_MMS2_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga07efe60d8d7305b78085233ddaecb990">TIM_CR2_MMS2_0</a>)</td></tr>
<tr class="memitem:ga98299af57d50ec9a0dc1fbd3d4d04c39" id="r_ga98299af57d50ec9a0dc1fbd3d4d04c39"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga98299af57d50ec9a0dc1fbd3d4d04c39">TIM_TRGO2_OC5REF_RISING_OC6REF_RISING</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga3503937610adbf78153c1fcfa4bcd6ea">TIM_CR2_MMS2_3</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gaa49670c71a446e5201994716b08b1527">TIM_CR2_MMS2_2</a> |<a class="el" href="group___peripheral___registers___bits___definition.html#ga0248e35956d0d22ac66dcd67aab317c5">TIM_CR2_MMS2_1</a>)</td></tr>
<tr class="memitem:ga90aeea268dbf4be05e4d5f221f40da7c" id="r_ga90aeea268dbf4be05e4d5f221f40da7c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="#ga90aeea268dbf4be05e4d5f221f40da7c">TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING</a>&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga3503937610adbf78153c1fcfa4bcd6ea">TIM_CR2_MMS2_3</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gaa49670c71a446e5201994716b08b1527">TIM_CR2_MMS2_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga0248e35956d0d22ac66dcd67aab317c5">TIM_CR2_MMS2_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga07efe60d8d7305b78085233ddaecb990">TIM_CR2_MMS2_0</a>)</td></tr>
</table>
<a name="details" id="details"></a><h2 id="header-details" class="groupheader">Detailed Description</h2>
<a name="doc-define-members" id="doc-define-members"></a><h2 id="header-doc-define-members" class="groupheader">Macro Definition Documentation</h2>
<a id="gab9344703b3c1a7936f6b500a6bc26cb9" name="gab9344703b3c1a7936f6b500a6bc26cb9"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gab9344703b3c1a7936f6b500a6bc26cb9">&#9670;&#160;</a></span>TIM_TRGO2_ENABLE</h2>

<div class="memitem">
<div class="memproto">
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        <tr>
          <td class="memname">#define TIM_TRGO2_ENABLE&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga07efe60d8d7305b78085233ddaecb990">TIM_CR2_MMS2_0</a></td>
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</div><div class="memdoc">
<p>TIMx_CR1.CEN bit is used as trigger output (TRGO2) </p>

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<a id="ga6199721bcb0eb5f89dcd0b1055f7376f" name="ga6199721bcb0eb5f89dcd0b1055f7376f"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga6199721bcb0eb5f89dcd0b1055f7376f">&#9670;&#160;</a></span>TIM_TRGO2_OC1</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TRGO2_OC1&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga0248e35956d0d22ac66dcd67aab317c5">TIM_CR2_MMS2_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga07efe60d8d7305b78085233ddaecb990">TIM_CR2_MMS2_0</a>)</td>
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      </table>
</div><div class="memdoc">
<p>Capture or a compare match 1 is used as trigger output (TRGO2) </p>

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<a id="gabe44de11cdf3f6d151b0d4a4945db092" name="gabe44de11cdf3f6d151b0d4a4945db092"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gabe44de11cdf3f6d151b0d4a4945db092">&#9670;&#160;</a></span>TIM_TRGO2_OC1REF</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TRGO2_OC1REF&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#gaa49670c71a446e5201994716b08b1527">TIM_CR2_MMS2_2</a></td>
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      </table>
</div><div class="memdoc">
<p>OC1REF signal is used as trigger output (TRGO2) </p>

</div>
</div>
<a id="gaaa5b56f4c834853ccf048399f77fbb3b" name="gaaa5b56f4c834853ccf048399f77fbb3b"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaaa5b56f4c834853ccf048399f77fbb3b">&#9670;&#160;</a></span>TIM_TRGO2_OC2REF</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TRGO2_OC2REF&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gaa49670c71a446e5201994716b08b1527">TIM_CR2_MMS2_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga07efe60d8d7305b78085233ddaecb990">TIM_CR2_MMS2_0</a>)</td>
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</div><div class="memdoc">
<p>OC2REF signal is used as trigger output (TRGO2) </p>

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<a id="ga670369673955ede3e33074ad1897c64a" name="ga670369673955ede3e33074ad1897c64a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga670369673955ede3e33074ad1897c64a">&#9670;&#160;</a></span>TIM_TRGO2_OC3REF</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TRGO2_OC3REF&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gaa49670c71a446e5201994716b08b1527">TIM_CR2_MMS2_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga0248e35956d0d22ac66dcd67aab317c5">TIM_CR2_MMS2_1</a>)</td>
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</div><div class="memdoc">
<p>OC3REF signal is used as trigger output (TRGO2) </p>

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<a id="gaa307bb2aa7beb9f0ea43247a38ca7b36" name="gaa307bb2aa7beb9f0ea43247a38ca7b36"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaa307bb2aa7beb9f0ea43247a38ca7b36">&#9670;&#160;</a></span>TIM_TRGO2_OC4REF</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">#define TIM_TRGO2_OC4REF&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#gaa49670c71a446e5201994716b08b1527">TIM_CR2_MMS2_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga0248e35956d0d22ac66dcd67aab317c5">TIM_CR2_MMS2_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga07efe60d8d7305b78085233ddaecb990">TIM_CR2_MMS2_0</a>)</td>
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<p>OC4REF signal is used as trigger output (TRGO2) </p>

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<a id="ga202fe63f92ca564cb18995a11b3946b2" name="ga202fe63f92ca564cb18995a11b3946b2"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga202fe63f92ca564cb18995a11b3946b2">&#9670;&#160;</a></span>TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING</h2>

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          <td class="memname">#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga3503937610adbf78153c1fcfa4bcd6ea">TIM_CR2_MMS2_3</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gaa49670c71a446e5201994716b08b1527">TIM_CR2_MMS2_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga07efe60d8d7305b78085233ddaecb990">TIM_CR2_MMS2_0</a>)</td>
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<p>OC4REF rising or OC6REF falling edges generate pulses on TRGO2 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga367b1addfd2f36bb8ed29e8e70e57024">&#9670;&#160;</a></span>TIM_TRGO2_OC4REF_RISING_OC6REF_RISING</h2>

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          <td class="memname">#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga3503937610adbf78153c1fcfa4bcd6ea">TIM_CR2_MMS2_3</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gaa49670c71a446e5201994716b08b1527">TIM_CR2_MMS2_2</a>)</td>
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<p>OC4REF or OC6REF rising edges generate pulses on TRGO2 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga0916f567135c5ee60031da2d146ad10b">&#9670;&#160;</a></span>TIM_TRGO2_OC4REF_RISINGFALLING</h2>

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          <td class="memname">#define TIM_TRGO2_OC4REF_RISINGFALLING&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga3503937610adbf78153c1fcfa4bcd6ea">TIM_CR2_MMS2_3</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga0248e35956d0d22ac66dcd67aab317c5">TIM_CR2_MMS2_1</a>)</td>
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<p>OC4REF rising or falling edges generate pulses on TRGO2 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga9609da1787a7dcde257de6f96dabed4c">&#9670;&#160;</a></span>TIM_TRGO2_OC5REF</h2>

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          <td class="memname">#define TIM_TRGO2_OC5REF&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga3503937610adbf78153c1fcfa4bcd6ea">TIM_CR2_MMS2_3</a></td>
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<p>OC5REF signal is used as trigger output (TRGO2) </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga90aeea268dbf4be05e4d5f221f40da7c">&#9670;&#160;</a></span>TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING</h2>

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          <td class="memname">#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga3503937610adbf78153c1fcfa4bcd6ea">TIM_CR2_MMS2_3</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gaa49670c71a446e5201994716b08b1527">TIM_CR2_MMS2_2</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga0248e35956d0d22ac66dcd67aab317c5">TIM_CR2_MMS2_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga07efe60d8d7305b78085233ddaecb990">TIM_CR2_MMS2_0</a>)</td>
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<p>OC5REF or OC6REF rising edges generate pulses on TRGO2 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga98299af57d50ec9a0dc1fbd3d4d04c39">&#9670;&#160;</a></span>TIM_TRGO2_OC5REF_RISING_OC6REF_RISING</h2>

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          <td class="memname">#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga3503937610adbf78153c1fcfa4bcd6ea">TIM_CR2_MMS2_3</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#gaa49670c71a446e5201994716b08b1527">TIM_CR2_MMS2_2</a> |<a class="el" href="group___peripheral___registers___bits___definition.html#ga0248e35956d0d22ac66dcd67aab317c5">TIM_CR2_MMS2_1</a>)</td>
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<p>OC5REF or OC6REF rising edges generate pulses on TRGO2 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gae88c0c9c55ffb739dada0bdea37a809d">&#9670;&#160;</a></span>TIM_TRGO2_OC6REF</h2>

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          <td class="memname">#define TIM_TRGO2_OC6REF&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga3503937610adbf78153c1fcfa4bcd6ea">TIM_CR2_MMS2_3</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga07efe60d8d7305b78085233ddaecb990">TIM_CR2_MMS2_0</a>)</td>
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<p>OC6REF signal is used as trigger output (TRGO2) </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gaefa63d8189e6e6fcd592fcf4af8aa416">&#9670;&#160;</a></span>TIM_TRGO2_OC6REF_RISINGFALLING</h2>

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          <td class="memname">#define TIM_TRGO2_OC6REF_RISINGFALLING&#160;&#160;&#160;(<a class="el" href="group___peripheral___registers___bits___definition.html#ga3503937610adbf78153c1fcfa4bcd6ea">TIM_CR2_MMS2_3</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga0248e35956d0d22ac66dcd67aab317c5">TIM_CR2_MMS2_1</a> | <a class="el" href="group___peripheral___registers___bits___definition.html#ga07efe60d8d7305b78085233ddaecb990">TIM_CR2_MMS2_0</a>)</td>
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<p>OC6REF rising or falling edges generate pulses on TRGO2 </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga1cbae68386015bde2e2087787d31a77f">&#9670;&#160;</a></span>TIM_TRGO2_RESET</h2>

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          <td class="memname">#define TIM_TRGO2_RESET&#160;&#160;&#160;0x00000000U</td>
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<p>TIMx_EGR.UG bit is used as trigger output (TRGO2) </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga7c09a032f333bd3c1896e53f8c476303">&#9670;&#160;</a></span>TIM_TRGO2_UPDATE</h2>

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          <td class="memname">#define TIM_TRGO2_UPDATE&#160;&#160;&#160;<a class="el" href="group___peripheral___registers___bits___definition.html#ga0248e35956d0d22ac66dcd67aab317c5">TIM_CR2_MMS2_1</a></td>
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<p>Update event is used as trigger output (TRGO2) </p>

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